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The-OpenROAD-Project / OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 784 301 Built by

10 stars this week

efabless / caravel_user_project

https://caravel-user-project.readthedocs.io

Verilog 112 267 Built by

1 star this week

ucb-bar / nvdla-wrapper

Wraps the NVDLA project for Chipyard integration

Verilog 13 7 Built by

0 stars this week

ucb-bar / sha3

Verilog 69 17 Built by

0 stars this week

chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Verilog 65 41 Built by

0 stars this week

nvdla / hw

RTL, Cmodel, and testbench for NVDLA

Verilog 1,424 511 Built by

4 stars this week

RapidSilicon / litex_reference_designs

Litex Reference Designs provides reference designs created out of IP Catalog using Litex integration capabilities.

Verilog 6 Built by

0 stars this week

IObundle / iob-lib

Verilog 16 19 Built by

0 stars this week

IObundle / iob-cache

Verilog configurable cache

Verilog 103 26 Built by

1 star this week

IObundle / iob-picorv32

IOb_SoC version of the Picorv32 RISC-V Verilog IP core

Verilog 10 12 Built by

0 stars this week

analogdevicesinc / hdl

HDL libraries and projects

Verilog 1,123 1,349 Built by

3 stars this week

EttusResearch / uhd

The USRP™ Hardware Driver Repository

Verilog 771 590 Built by

3 stars this week

IObundle / iob-axi

Verilog 5 4 Built by

0 stars this week

Xilinx / libsystemctlm-soc

SystemC/TLM-2.0 Co-simulation framework

Verilog 132 46 Built by

1 star this week

alexforencich / verilog-ethernet

Verilog Ethernet components for FPGA implementation

Verilog 1,422 478 Built by

7 stars this week

alexforencich / verilog-axi

Verilog AXI components for FPGA implementation

Verilog 874 326 Built by

8 stars this week

IObundle / iob-mem

Verilog behavioral description of various memories

Verilog 27 19 Built by

0 stars this week

bespoke-silicon-group / bsg_manycore

Tile based architecture designed for computing efficiency, scalability and generality

Verilog 177 47 Built by

1 star this week

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Verilog 868 301 Built by

1 star this week