openhwgroup / cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
A Linux-capable RISC-V multicore for and by the world
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
AXI X-Bar
IPs for control-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
Pipelines the AXI path with FIFOs
IP Blocks to Support Design, Prototyping, and Verification of PULP on FPGAs
open-source Ethenet media access controller for Ariane on Genesys-2
Simple single-port AXI memory interface
AXI Adapter(s) for RISC-V Atomic Operations
APB Timer Unit
OpenTitan: Open source silicon root of trust
[UNRELEASED] FP div/sqrt unit for transprecision
RISC-V Debug Support for our PULP RISC-V Cores
Generic Register Interface (contains various adatpers)