From a7fe922b98bb45be7dce7c1cfe668ec27eeddc74 Mon Sep 17 00:00:00 2001 From: Dimitry Andric Date: Wed, 17 Aug 2016 19:33:52 +0000 Subject: Vendor import of llvm release_39 branch r278877: https://llvm.org/svn/llvm-project/llvm/branches/release_39@278877 --- docs/CodeGenerator.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'docs/CodeGenerator.rst') diff --git a/docs/CodeGenerator.rst b/docs/CodeGenerator.rst index 6a54343dfba6..2f5a27c00af3 100644 --- a/docs/CodeGenerator.rst +++ b/docs/CodeGenerator.rst @@ -436,7 +436,7 @@ For example, consider this simple LLVM example: The X86 instruction selector might produce this machine code for the ``div`` and ``ret``: -.. code-block:: llvm +.. code-block:: text ;; Start of div %EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX @@ -453,7 +453,7 @@ By the end of code generation, the register allocator would coalesce the registers and delete the resultant identity moves producing the following code: -.. code-block:: llvm +.. code-block:: text ;; X is in EAX, Y is in ECX mov %EAX, %EDX @@ -965,7 +965,7 @@ target code. For example, consider the following LLVM fragment: This LLVM code corresponds to a SelectionDAG that looks basically like this: -.. code-block:: llvm +.. code-block:: text (fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z) -- cgit v1.3