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authorDimitry Andric <dim@FreeBSD.org>2024-09-22 09:37:02 +0000
committerDimitry Andric <dim@FreeBSD.org>2024-09-22 09:37:02 +0000
commit1de139fdd502e836552eba1049a42b45514d8f7b (patch)
tree9418bf14cdd3b0ea4bf5dbe50ee2ec4550264ddc /llvm/lib/TargetParser/Host.cpp
parent7432c96084d72c631f1e5ddf1cc2e24fd9c92482 (diff)
Vendor import of llvm-project branch release/19.x llvmorg-19.1.0-0-ga4bf6cd7cfb1, a.k.a. 19.1.0 release.vendor/llvm-project/llvmorg-19.1.0-0-ga4bf6cd7cfb1
Diffstat (limited to 'llvm/lib/TargetParser/Host.cpp')
-rw-r--r--llvm/lib/TargetParser/Host.cpp19
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 7e637cba4cfb..865b6a44adbb 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1213,6 +1213,25 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
break; // "znver4"
}
break; // family 19h
+ case 26:
+ CPU = "znver5";
+ *Type = X86::AMDFAM1AH;
+ if (Model <= 0x77) {
+ // Models 00h-0Fh (Breithorn).
+ // Models 10h-1Fh (Breithorn-Dense).
+ // Models 20h-2Fh (Strix 1).
+ // Models 30h-37h (Strix 2).
+ // Models 38h-3Fh (Strix 3).
+ // Models 40h-4Fh (Granite Ridge).
+ // Models 50h-5Fh (Weisshorn).
+ // Models 60h-6Fh (Krackan1).
+ // Models 70h-77h (Sarlak).
+ CPU = "znver5";
+ *Subtype = X86::AMDFAM1AH_ZNVER5;
+ break; // "znver5"
+ }
+ break;
+
default:
break; // Unknown AMD CPU.
}