Import llvm 3.7.0 release (r246257). - src

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author	Dimitry Andric <dim@FreeBSD.org>	2015-09-06 18:34:38 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2015-09-06 18:34:38 +0000
commit	69156b4c20249e7800cc09e0eef0beb3d15ac1ad (patch)
tree	461d3cf041290f4a99740d540bf0973d6084f98e /lib/Target/X86
parent	ee8648bdac07986a0f1ec897b02ec82a2f144d46 (diff)

Import llvm 3.7.0 release (r246257).vendor/llvm/llvm-release_370-r246257

Notes

svn path=/vendor/llvm/dist/; revision=287510 svn path=/vendor/llvm/llvm-release_370-r246257/; revision=287511; tag=vendor/llvm/llvm-release_370-r246257

Diffstat (limited to 'lib/Target/X86')

-rw-r--r--

lib/Target/X86/AsmParser/X86AsmParser.cpp

-rw-r--r--

lib/Target/X86/X86FloatingPoint.cpp

-rw-r--r--

lib/Target/X86/X86FrameLowering.cpp

-rw-r--r--

lib/Target/X86/X86ISelLowering.cpp

-rw-r--r--

lib/Target/X86/X86InstrInfo.cpp

-rw-r--r--

lib/Target/X86/X86InstrSSE.td

6 files changed, 90 insertions, 76 deletions

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 418f0431e1d8..bca059d8c383 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp

@@ -681,6 +681,9 @@ private:

std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);

std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);

+ void AddDefaultSrcDestOperands(

+ OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,

+ std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);

std::unique_ptr<X86Operand> ParseOperand();

std::unique_ptr<X86Operand> ParseATTOperand();

std::unique_ptr<X86Operand> ParseIntelOperand();

@@ -1014,6 +1017,19 @@ std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {

Loc, Loc, 0);

}

+void X86AsmParser::AddDefaultSrcDestOperands(

+ OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,

+ std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {

+ if (isParsingIntelSyntax()) {

+ Operands.push_back(std::move(Dst));

+ Operands.push_back(std::move(Src));

+ }

+ else {

+ Operands.push_back(std::move(Src));

+ Operands.push_back(std::move(Dst));

+ }

std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {

if (isParsingIntelSyntax())

return ParseIntelOperand();

@@ -2228,26 +2244,18 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,

if (Name.startswith("ins") && Operands.size() == 1 &&

(Name == "insb" || Name == "insw" || Name == "insl" ||

Name == "insd" )) {

- if (isParsingIntelSyntax()) {

- Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));

- Operands.push_back(DefaultMemDIOperand(NameLoc));

- } else {

- Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));

- Operands.push_back(DefaultMemDIOperand(NameLoc));

- }

+ AddDefaultSrcDestOperands(Operands,

+ X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),

+ DefaultMemDIOperand(NameLoc));

}

// Append default arguments to "outs[bwld]"

if (Name.startswith("outs") && Operands.size() == 1 &&

(Name == "outsb" || Name == "outsw" || Name == "outsl" ||

Name == "outsd" )) {

- if (isParsingIntelSyntax()) {

- Operands.push_back(DefaultMemSIOperand(NameLoc));

- Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));

- } else {

- Operands.push_back(DefaultMemSIOperand(NameLoc));

- Operands.push_back(X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));

- }

+ AddDefaultSrcDestOperands(Operands,

+ DefaultMemSIOperand(NameLoc),

+ X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));

}

// Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate

@@ -2279,13 +2287,9 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,

(Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||

Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {

if (Operands.size() == 1) {

- if (isParsingIntelSyntax()) {

- Operands.push_back(DefaultMemSIOperand(NameLoc));

- Operands.push_back(DefaultMemDIOperand(NameLoc));

- } else {

- Operands.push_back(DefaultMemDIOperand(NameLoc));

- Operands.push_back(DefaultMemSIOperand(NameLoc));

- }

+ AddDefaultSrcDestOperands(Operands,

+ DefaultMemDIOperand(NameLoc),

+ DefaultMemSIOperand(NameLoc));

} else if (Operands.size() == 3) {

X86Operand &Op = (X86Operand &)*Operands[1];

X86Operand &Op2 = (X86Operand &)*Operands[2];

@@ -2305,13 +2309,9 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,

if (Operands.size() == 1) {

if (Name == "movsd")

Operands.back() = X86Operand::CreateToken("movsl", NameLoc);

- if (isParsingIntelSyntax()) {

- Operands.push_back(DefaultMemDIOperand(NameLoc));

- Operands.push_back(DefaultMemSIOperand(NameLoc));

- } else {

- Operands.push_back(DefaultMemSIOperand(NameLoc));

- Operands.push_back(DefaultMemDIOperand(NameLoc));

- }

+ AddDefaultSrcDestOperands(Operands,

+ DefaultMemSIOperand(NameLoc),

+ DefaultMemDIOperand(NameLoc));

} else if (Operands.size() == 3) {

X86Operand &Op = (X86Operand &)*Operands[1];

X86Operand &Op2 = (X86Operand &)*Operands[2];

diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 36a8cdbab55b..40b9c8a863a3 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp

@@ -301,9 +301,8 @@ bool FPS::runOnMachineFunction(MachineFunction &MF) {

bool FPIsUsed = false;

static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!");

- const MachineRegisterInfo &MRI = MF.getRegInfo();

for (unsigned i = 0; i <= 6; ++i)

- if (!MRI.reg_nodbg_empty(X86::FP0 + i)) {

+ if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {

FPIsUsed = true;

break;

}

diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp
index 2a35c4cf31f3..3a21b57f0157 100644
--- a/lib/Target/X86/X86FrameLowering.cpp
+++ b/lib/Target/X86/X86FrameLowering.cpp

@@ -1682,6 +1682,8 @@ void X86FrameLowering::adjustForSegmentedStacks(

.addImm(StackSize);

BuildMI(allocMBB, DL, TII.get(MOVri), Reg11)

.addImm(X86FI->getArgumentStackSize());

+ MF.getRegInfo().setPhysRegUsed(Reg10);

+ MF.getRegInfo().setPhysRegUsed(Reg11);

} else {

BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))

.addImm(X86FI->getArgumentStackSize());

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 6e22ab30057c..71ccb1ab1e55 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp

@@ -12640,24 +12640,29 @@ static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {

if (User->getOpcode() == ISD::FNEG)

return Op;

- SDValue Op0 = Op.getOperand(0);

- bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);

SDLoc dl(Op);

MVT VT = Op.getSimpleValueType();

- // Assume scalar op for initialization; update for vector if needed.

- // Note that there are no scalar bitwise logical SSE/AVX instructions, so we

- // generate a 16-byte vector constant and logic op even for the scalar case.

- // Using a 16-byte mask allows folding the load of the mask with

- // the logic op, so it can save (~4 bytes) on code size.

- MVT EltVT = VT;

- unsigned NumElts = VT == MVT::f64 ? 2 : 4;

// FIXME: Use function attribute "OptimizeForSize" and/or CodeGenOpt::Level to

// decide if we should generate a 16-byte constant mask when we only need 4 or

// 8 bytes for the scalar case.

+ MVT LogicVT;

+ MVT EltVT;

+ unsigned NumElts;

if (VT.isVector()) {

+ LogicVT = VT;

EltVT = VT.getVectorElementType();

NumElts = VT.getVectorNumElements();

+ } else {

+ // There are no scalar bitwise logical SSE/AVX instructions, so we

+ // generate a 16-byte vector constant and logic op even for the scalar case.

+ // Using a 16-byte mask allows folding the load of the mask with

+ // the logic op, so it can save (~4 bytes) on code size.

+ LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;

+ EltVT = VT;

+ NumElts = (VT == MVT::f64) ? 2 : 4;

}

unsigned EltBits = EltVT.getSizeInBits();

@@ -12670,26 +12675,25 @@ static SDValue LowerFABSorFNEG(SDValue Op, SelectionDAG &DAG) {

const TargetLowering &TLI = DAG.getTargetLoweringInfo();

SDValue CPIdx = DAG.getConstantPool(C, TLI.getPointerTy(DAG.getDataLayout()));

unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();

- SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,

+ SDValue Mask = DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,

MachinePointerInfo::getConstantPool(),

false, false, false, Alignment);

- if (VT.isVector()) {

- // For a vector, cast operands to a vector type, perform the logic op,

- // and cast the result back to the original value type.

- MVT VecVT = MVT::getVectorVT(MVT::i64, VT.getSizeInBits() / 64);

- SDValue MaskCasted = DAG.getBitcast(VecVT, Mask);

- SDValue Operand = IsFNABS ? DAG.getBitcast(VecVT, Op0.getOperand(0))

- : DAG.getBitcast(VecVT, Op0);

- unsigned BitOp = IsFABS ? ISD::AND : IsFNABS ? ISD::OR : ISD::XOR;

- return DAG.getBitcast(VT,

- DAG.getNode(BitOp, dl, VecVT, Operand, MaskCasted));

- }

- // If not vector, then scalar.

- unsigned BitOp = IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;

+ SDValue Op0 = Op.getOperand(0);

+ bool IsFNABS = !IsFABS && (Op0.getOpcode() == ISD::FABS);

+ unsigned LogicOp =

+ IsFABS ? X86ISD::FAND : IsFNABS ? X86ISD::FOR : X86ISD::FXOR;

SDValue Operand = IsFNABS ? Op0.getOperand(0) : Op0;

- return DAG.getNode(BitOp, dl, VT, Operand, Mask);

+ if (VT.isVector())

+ return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);

+ // For the scalar case extend to a 128-bit vector, perform the logic op,

+ // and extract the scalar result back out.

+ Operand = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Operand);

+ SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask);

+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, LogicNode,

+ DAG.getIntPtrConstant(0, dl));

}

static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {

@@ -12729,10 +12733,16 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {

Constant *C = ConstantVector::get(CV);

auto PtrVT = TLI.getPointerTy(DAG.getDataLayout());

SDValue CPIdx = DAG.getConstantPool(C, PtrVT, 16);

- SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx,

+ // Perform all logic operations as 16-byte vectors because there are no

+ // scalar FP logic instructions in SSE. This allows load folding of the

+ // constants into the logic instructions.

+ MVT LogicVT = (VT == MVT::f64) ? MVT::v2f64 : MVT::v4f32;

+ SDValue Mask1 = DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,

MachinePointerInfo::getConstantPool(),

false, false, false, 16);

- SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1);

+ Op1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op1);

+ SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op1, Mask1);

// Next, clear the sign bit from the first operand (magnitude).

// If it's a constant, we can clear it here.

@@ -12740,7 +12750,8 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {

APFloat APF = Op0CN->getValueAPF();

// If the magnitude is a positive zero, the sign bit alone is enough.

if (APF.isPosZero())

- return SignBit;

+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, SignBit,

+ DAG.getIntPtrConstant(0, dl));

APF.clearSign();

CV[0] = ConstantFP::get(*Context, APF);

} else {

@@ -12750,15 +12761,18 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {

}

C = ConstantVector::get(CV);

CPIdx = DAG.getConstantPool(C, PtrVT, 16);

- SDValue Val = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,

+ SDValue Val = DAG.getLoad(LogicVT, dl, DAG.getEntryNode(), CPIdx,

MachinePointerInfo::getConstantPool(),

false, false, false, 16);

// If the magnitude operand wasn't a constant, we need to AND out the sign.

- if (!isa<ConstantFPSDNode>(Op0))

- Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Val);

+ if (!isa<ConstantFPSDNode>(Op0)) {

+ Op0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LogicVT, Op0);

+ Val = DAG.getNode(X86ISD::FAND, dl, LogicVT, Op0, Val);

+ }

// OR the magnitude value with the sign bit.

- return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit);

+ Val = DAG.getNode(X86ISD::FOR, dl, LogicVT, Val, SignBit);

+ return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SrcVT, Val,

+ DAG.getIntPtrConstant(0, dl));

}

static SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) {

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 786150760b93..cf68ef053361 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp

@@ -956,18 +956,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)

{ X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },

{ X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },

- // FIXME: We should not be folding Fs* scalar loads into vector

- // instructions because the vector instructions require vector-sized

- // loads. Lowering should create vector-sized instructions (the Fv*

- // variants below) to allow load folding.

- { X86::FsANDNPDrr, X86::FsANDNPDrm, TB_ALIGN_16 },

- { X86::FsANDNPSrr, X86::FsANDNPSrm, TB_ALIGN_16 },

- { X86::FsANDPDrr, X86::FsANDPDrm, TB_ALIGN_16 },

- { X86::FsANDPSrr, X86::FsANDPSrm, TB_ALIGN_16 },

- { X86::FsORPDrr, X86::FsORPDrm, TB_ALIGN_16 },

- { X86::FsORPSrr, X86::FsORPSrm, TB_ALIGN_16 },

- { X86::FsXORPDrr, X86::FsXORPDrm, TB_ALIGN_16 },

- { X86::FsXORPSrr, X86::FsXORPSrm, TB_ALIGN_16 },

+ // Do not fold Fs* scalar logical op loads because there are no scalar

+ // load variants for these instructions. When folded, the load is required

+ // to be 128-bits, so the load size would not match.

{ X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },

{ X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index a5ff9edf05a3..99386b0658ad 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td

@@ -2919,6 +2919,14 @@ multiclass sse12_fp_packed_vector_logical_alias<

defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,

VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,

PD, VEX_4V;

+ defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,

+ VR256, v8f32, f256mem, loadv8f32, SSEPackedSingle, itins, 0>,

+ PS, VEX_4V, VEX_L;

+ defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,

+ VR256, v4f64, f256mem, loadv4f64, SSEPackedDouble, itins, 0>,

+ PD, VEX_4V, VEX_L;

}

let Constraints = "$src1 = $dst" in {