Vendor import of llvm trunk r303571: - src

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author	Dimitry Andric <dim@FreeBSD.org>	2017-05-22 19:43:28 +0000
committer	Dimitry Andric <dim@FreeBSD.org>	2017-05-22 19:43:28 +0000
commit	b5630dbadf9a2a06754194387d6b0fd9962a67f1 (patch)
tree	3fe1e2bc0dc2823ab21f06959fbb3eaca317ea29 /lib/Target/PowerPC
parent	7af96fb3afd6725a2824a0a5ca5dad34e5e0b056 (diff)

Vendor import of llvm trunk r303571:vendor/llvm/llvm-trunk-r303571

https://llvm.org/svn/llvm-project/llvm/trunk@303571

Notes

svn path=/vendor/llvm/dist/; revision=318663 svn path=/vendor/llvm/llvm-trunk-r303571/; revision=318664; tag=vendor/llvm/llvm-trunk-r303571

Diffstat (limited to 'lib/Target/PowerPC')

-rw-r--r--

lib/Target/PowerPC/PPCISelLowering.cpp

-rw-r--r--

lib/Target/PowerPC/PPCInstrAltivec.td

-rw-r--r--

lib/Target/PowerPC/PPCInstrInfo.cpp

-rw-r--r--

lib/Target/PowerPC/PPCTargetMachine.cpp

4 files changed, 68 insertions, 7 deletions

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 144aea850833..e65b1f1aa0a5 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -689,6 +689,14 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,

setOperationAction(ISD::SRA, MVT::v2i64, Legal);

setOperationAction(ISD::SRL, MVT::v2i64, Legal);

+ // 128 bit shifts can be accomplished via 3 instructions for SHL and

+ // SRL, but not for SRA because of the instructions available:

+ // VS{RL} and VS{RL}O. However due to direct move costs, it's not worth

+ // doing

+ setOperationAction(ISD::SHL, MVT::v1i128, Expand);

+ setOperationAction(ISD::SRL, MVT::v1i128, Expand);

+ setOperationAction(ISD::SRA, MVT::v1i128, Expand);

setOperationAction(ISD::SETCC, MVT::v2i64, Legal);

}

else {

@@ -742,6 +750,13 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,

if (Subtarget.hasP9Vector()) {

setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);

setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);

+ // 128 bit shifts can be accomplished via 3 instructions for SHL and

+ // SRL, but not for SRA because of the instructions available:

+ // VS{RL} and VS{RL}O.

+ setOperationAction(ISD::SHL, MVT::v1i128, Legal);

+ setOperationAction(ISD::SRL, MVT::v1i128, Legal);

+ setOperationAction(ISD::SRA, MVT::v1i128, Expand);

}

diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td
index e14d18fd5433..5465b5f2d66c 100644
--- a/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/lib/Target/PowerPC/PPCInstrAltivec.td

@@ -987,12 +987,16 @@ def : Pat<(v8i16 (shl v8i16:$vA, v8i16:$vB)),

(v8i16 (VSLH $vA, $vB))>;

def : Pat<(v4i32 (shl v4i32:$vA, v4i32:$vB)),

(v4i32 (VSLW $vA, $vB))>;

+def : Pat<(v1i128 (shl v1i128:$vA, v1i128:$vB)),

+ (v1i128 (VSL (VSLO $vA, $vB), (VSPLTB 15, $vB)))>;

def : Pat<(v16i8 (PPCshl v16i8:$vA, v16i8:$vB)),

(v16i8 (VSLB $vA, $vB))>;

def : Pat<(v8i16 (PPCshl v8i16:$vA, v8i16:$vB)),

(v8i16 (VSLH $vA, $vB))>;

def : Pat<(v4i32 (PPCshl v4i32:$vA, v4i32:$vB)),

(v4i32 (VSLW $vA, $vB))>;

+def : Pat<(v1i128 (PPCshl v1i128:$vA, v1i128:$vB)),

+ (v1i128 (VSL (VSLO $vA, $vB), (VSPLTB 15, $vB)))>;

def : Pat<(v16i8 (srl v16i8:$vA, v16i8:$vB)),

(v16i8 (VSRB $vA, $vB))>;

@@ -1000,12 +1004,16 @@ def : Pat<(v8i16 (srl v8i16:$vA, v8i16:$vB)),

(v8i16 (VSRH $vA, $vB))>;

def : Pat<(v4i32 (srl v4i32:$vA, v4i32:$vB)),

(v4i32 (VSRW $vA, $vB))>;

+def : Pat<(v1i128 (srl v1i128:$vA, v1i128:$vB)),

+ (v1i128 (VSR (VSRO $vA, $vB), (VSPLTB 15, $vB)))>;

def : Pat<(v16i8 (PPCsrl v16i8:$vA, v16i8:$vB)),

(v16i8 (VSRB $vA, $vB))>;

def : Pat<(v8i16 (PPCsrl v8i16:$vA, v8i16:$vB)),

(v8i16 (VSRH $vA, $vB))>;

def : Pat<(v4i32 (PPCsrl v4i32:$vA, v4i32:$vB)),

(v4i32 (VSRW $vA, $vB))>;

+def : Pat<(v1i128 (PPCsrl v1i128:$vA, v1i128:$vB)),

+ (v1i128 (VSR (VSRO $vA, $vB), (VSPLTB 15, $vB)))>;

def : Pat<(v16i8 (sra v16i8:$vA, v16i8:$vB)),

(v16i8 (VSRAB $vA, $vB))>;

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 3afcec1248d5..46f103141bc1 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -1533,6 +1533,8 @@ bool PPCInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,

case PPC::FCMPUD:

SrcReg = MI.getOperand(1).getReg();

SrcReg2 = MI.getOperand(2).getReg();

+ Value = 0;

+ Mask = 0;

return true;

}

@@ -1591,9 +1593,12 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,

// We can perform this optimization, equality only, if MI is

// zero-extending.

+ // FIXME: Other possible target instructions include ANDISo and

+ // RLWINM aliases, such as ROTRWI, EXTLWI, SLWI and SRWI.

if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||

MIOpC == PPC::SLW || MIOpC == PPC::SLWo ||

MIOpC == PPC::SRW || MIOpC == PPC::SRWo ||

+ MIOpC == PPC::ANDIo ||

isZeroExtendingRotate) {

noSub = true;

equalityOnly = true;

@@ -1641,6 +1646,9 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,

break;

}

+ SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;

+ SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;

// There are two possible candidates which can be changed to set CR[01].

// One is MI, the other is a SUB instruction.

// For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).

@@ -1652,9 +1660,37 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,

// same BB as the comparison. This is to allow the check below to avoid calls

// (and other explicit clobbers); instead we should really check for these

// more explicitly (in at least a few predecessors).

- else if (MI->getParent() != CmpInstr.getParent() || Value != 0) {

- // PPC does not have a record-form SUBri.

+ else if (MI->getParent() != CmpInstr.getParent())

return false;

+ else if (Value != 0) {

+ // The record-form instructions set CR bit based on signed comparison against 0.

+ // We try to convert a compare against 1 or -1 into a compare against 0.

+ bool Success = false;

+ if (!equalityOnly && MRI->hasOneUse(CRReg)) {

+ MachineInstr *UseMI = &*MRI->use_instr_begin(CRReg);

+ if (UseMI->getOpcode() == PPC::BCC) {

+ PPC::Predicate Pred = (PPC::Predicate)UseMI->getOperand(0).getImm();

+ int16_t Immed = (int16_t)Value;

+ if (Immed == -1 && Pred == PPC::PRED_GT) {

+ // We convert "greater than -1" into "greater than or equal to 0",

+ // since we are assuming signed comparison by !equalityOnly

+ PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),

+ PPC::PRED_GE));

+ Success = true;

+ }

+ else if (Immed == 1 && Pred == PPC::PRED_LT) {

+ // We convert "less than 1" into "less than or equal to 0".

+ PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)),

+ PPC::PRED_LE));

+ Success = true;

+ }

+ // PPC does not have a record-form SUBri.

+ if (!Success)

+ return false;

}

// Search for Sub.

@@ -1720,15 +1756,14 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,

if (NewOpC == -1)

return false;

- SmallVector<std::pair<MachineOperand*, PPC::Predicate>, 4> PredsToUpdate;

- SmallVector<std::pair<MachineOperand*, unsigned>, 4> SubRegsToUpdate;

// If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP

// needs to be updated to be based on SUB. Push the condition code

// operands to OperandsToUpdate. If it is safe to remove CmpInstr, the

// condition code of these operands will be modified.

+ // Here, Value == 0 means we haven't converted comparison against 1 or -1 to

+ // comparison against 0, which may modify predicate.

bool ShouldSwap = false;

- if (Sub) {

+ if (Sub && Value == 0) {

ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&

Sub->getOperand(2).getReg() == SrcReg;

@@ -1765,6 +1800,9 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,

} else // We need to abort on a user we don't understand.

return false;

}

+ assert(!(Value != 0 && ShouldSwap) &&

+ "Non-zero immediate support and ShouldSwap"

+ "may conflict in updating predicate");

// Create a new virtual register to hold the value of the CR set by the

// record-form instruction. If the instruction was not previously in

diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 7806d45b5457..ddae5befee3e 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp

@@ -322,7 +322,7 @@ TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {

void PPCPassConfig::addIRPasses() {

if (TM->getOptLevel() != CodeGenOpt::None)

addPass(createPPCBoolRetToIntPass());

- addPass(createAtomicExpandPass(&getPPCTargetMachine()));

+ addPass(createAtomicExpandPass());

// For the BG/Q (or if explicitly requested), add explicit data prefetch

// intrinsics.