diff options
| author | Dimitry Andric <dim@FreeBSD.org> | 2017-12-02 12:46:23 +0000 |
|---|---|---|
| committer | Dimitry Andric <dim@FreeBSD.org> | 2017-12-02 12:46:23 +0000 |
| commit | edad5bcb76bf472a1487c0f3dd94a5914213a647 (patch) | |
| tree | 63c3f98843d0debbfd390005cf8e05250cd3fe28 /lib/Target/Mips/MipsSEInstrInfo.cpp | |
| parent | 0bc1bd0d3931803dc6a26d35758f93527359bcdb (diff) | |
Vendor import of llvm release_50 branch r319231:vendor/llvm/llvm-release_50-r319231
Notes
svn path=/vendor/llvm/dist/; revision=326460
svn path=/vendor/llvm/llvm-release_50-r319231/; revision=326461; tag=vendor/llvm/llvm-release_50-r319231
Diffstat (limited to 'lib/Target/Mips/MipsSEInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsSEInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsSEInstrInfo.cpp b/lib/Target/Mips/MipsSEInstrInfo.cpp index ee074798563d..d2c21691abb0 100644 --- a/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -226,6 +226,8 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Opc = Mips::SW; else if (Mips::HI64RegClass.hasSubClassEq(RC)) Opc = Mips::SD; + else if (Mips::DSPRRegClass.hasSubClassEq(RC)) + Opc = Mips::SWDSP; // Hi, Lo are normally caller save but they are callee save // for interrupt handling. @@ -302,6 +304,8 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Opc = Mips::LW; else if (Mips::LO64RegClass.hasSubClassEq(RC)) Opc = Mips::LD; + else if (Mips::DSPRRegClass.hasSubClassEq(RC)) + Opc = Mips::LWDSP; assert(Opc && "Register class not handled!"); |