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authorDimitry Andric <dim@FreeBSD.org>2017-12-02 12:46:23 +0000
committerDimitry Andric <dim@FreeBSD.org>2017-12-02 12:46:23 +0000
commitedad5bcb76bf472a1487c0f3dd94a5914213a647 (patch)
tree63c3f98843d0debbfd390005cf8e05250cd3fe28 /lib/Target/ARM/ARMAsmPrinter.cpp
parent0bc1bd0d3931803dc6a26d35758f93527359bcdb (diff)
Vendor import of llvm release_50 branch r319231:vendor/llvm/llvm-release_50-r319231
Notes
svn path=/vendor/llvm/dist/; revision=326460 svn path=/vendor/llvm/llvm-release_50-r319231/; revision=326461; tag=vendor/llvm/llvm-release_50-r319231
Diffstat (limited to 'lib/Target/ARM/ARMAsmPrinter.cpp')
-rw-r--r--lib/Target/ARM/ARMAsmPrinter.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 582153daebde..b24d3420d1d9 100644
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1276,6 +1276,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Add 's' bit operand (always reg0 for this)
.addReg(0));
+ assert(Subtarget->hasV4TOps());
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
.addReg(MI->getOperand(0).getReg()));
return;
@@ -1896,6 +1897,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
.addImm(ARMCC::AL)
.addReg(0));
+ assert(Subtarget->hasV4TOps());
EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
.addReg(ScratchReg)
// Predicate.