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authorDimitry Andric <dim@FreeBSD.org>2017-12-02 12:46:23 +0000
committerDimitry Andric <dim@FreeBSD.org>2017-12-02 12:46:23 +0000
commitedad5bcb76bf472a1487c0f3dd94a5914213a647 (patch)
tree63c3f98843d0debbfd390005cf8e05250cd3fe28 /lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
parent0bc1bd0d3931803dc6a26d35758f93527359bcdb (diff)
Vendor import of llvm release_50 branch r319231:vendor/llvm/llvm-release_50-r319231
Notes
svn path=/vendor/llvm/dist/; revision=326460 svn path=/vendor/llvm/llvm-release_50-r319231/; revision=326461; tag=vendor/llvm/llvm-release_50-r319231
Diffstat (limited to 'lib/Target/AArch64/AArch64RedundantCopyElimination.cpp')
-rw-r--r--lib/Target/AArch64/AArch64RedundantCopyElimination.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
index 4e65c0ab6011..22c11c7276d2 100644
--- a/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+++ b/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
@@ -167,6 +167,9 @@ AArch64RedundantCopyElimination::knownRegValInBlock(
// CMP is an alias for SUBS with a dead destination register.
case AArch64::SUBSWri:
case AArch64::SUBSXri: {
+ // Sometimes the first operand is a FrameIndex. Bail if tht happens.
+ if (!PredI.getOperand(1).isReg())
+ return None;
MCPhysReg SrcReg = PredI.getOperand(1).getReg();
// Must not be a symbolic immediate.