@hackage clash-lib1.10.0
Clash: a functional hardware description language - As a library
Installation
Tested Compilers
Dependencies (50)
- aeson >=2.0.0.0 && <2.3
- aeson-pretty >=0.8 && <0.9
- ansi-terminal >=0.8.0.0 && <1.2
- array
- async >=2.2.0 && <2.3
- attoparsec >=0.10.4.0 && <0.15 Show all…
Dependents (11)
@hackage/clash-verilog, @hackage/clash-systemverilog, @hackage/clash-vhdl, @hackage/clash-vexriscv, @hackage/acme-everything, @hackage/clash-ghc, Show all…
Package Flags
debug
(off by default)
Build a debug compiler
unittests
(on by default)
You can disable testing with unittests using `-f-unittests`.
doctests
(on by default)
You can disable testing with doctests using `-f-doctests`.
workaround-ghc-mmap-crash
(off by default)
Only use this flag when hit by GHC bug #19421. See clash-compiler PR #2444.
clash-lib - Clash compiler, as a library
- See the LICENSE file for license and copyright details
Clash - A functional hardware description language
Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
Features of Clash:
-
Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
-
Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
-
Higher-order functions, with type inference, result in designs that are fully parametric by default.
-
Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops. -
Support for multiple clock domains, with type safe clock domain crossing.
Open-source community
Clash benefits from an active community. Whether you need a question answered or want to contribute to open-source features, browse the features below to make the most of Clash.