# Source: covered
# Package: covered-doc
# Versions: covered-doc (0.7.10-1), covered-doc (0.7.10-2), covered-doc (0.7.10-3), covered-doc (0.7.10-3.1), covered-doc (0.7.10-4), covered-doc (0.7.10-5), covered-doc (0.7.10-6), covered-doc (0.7.10-7), covered-doc (0.7.10-8), covered-doc (0.7.10-9), covered-doc (0.7.6-1), covered-doc (0.7.7-1), covered-doc (0.7.8-1), covered-doc (0.7.8-2), covered-doc (0.7.9-1)
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Description: Verilog code coverage analysis tool - documentation
 Covered is a Verilog code coverage utility that reads in a Verilog design and
 a generated VCD/LXT dumpfile from that design and generates a coverage file
 that can be merged with other coverage files or used to create a coverage
 report. Covered also contains the GUI coverage report utility that reads in a
 coverage file to allow interactive coverage discovery. Areas of coverage
 measured by Covered are: line, toggle, memory, combinational logic, FSM
 state/state-transition and assertion coverage.
 .
 This package contains the documentation.
Description-es: <trans>
 <trans>
 .
 Este paquete contiene la documentación.

# other Descriptions of the covered-doc package with a translation in es:
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